Computer Architecture & Organization: Notes & Study Guide
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Computer Architecture and Organization(FA 2020_EEL4768C.01FX ENGR)
I will take all notes on the class here and then build a study guide at the end
Overview
Semester: Fall 2020
School: Florida Polytechnic University
Textbook: Digital Design and Computer Architecture, 2nd Edition
Microprocessors have revolutionized our world–Cell phones, Internet, rapid advances in medicine, etc.
The semiconductor industry has grown from $21 billion in 1985 to $300 billion in 2011
Abstraction — Hiding details when they aren’t important
Discipline — Intentionally restrict design choices
Hierarchy — Intentionally restrict design choices
Modularity — Having well-defined functions and interfaces
Regularity — Encouraging uniformity, so modules can be easily reused
Notes
Chapter
Study Guide
Exam 1:
Our first exam is on 09/25/2020 from 6–8pm
It will be covering:
Memory Capacity — MIPS memory is byte-addressable, which means that each memory address references an 8-bit quantity. The MIPS architecture can support up to 32 address lines.
Binary to hexadecimal:
Binary to Octal:
- 2-s complement
5. Give three examples from the MIPS architecture of each of the architecture design principles:
(1) Simplicity favors regularity:
- Each instruction has a 6-bit opcode.
- MIPS has only 3 instruction formats (R-Type, I-Type, J-Type).
- Each instruction format has the same number and order of operands (they differ only in the opcode).
- Each instruction is the same size, making decoding hardware simple.
(2) Make the common case fast.
- Registers make the access to most recently accessed variables fast.
- The RISC (reduced instruction set computer) architecture, makes the common/simple instructions fast because the computer must handle only a small number of simple instructions.
- Most instructions require all 32 bits of an instruction, so all instructions are32 bits (even though some would have an advantage of a larger instructionsize and others a smaller instruction size).
- The instruction size is chosen tomake the common instructions fast.
(3) Smaller is faster.
- The register file has only 32 registers.
- The ISA (instruction set architecture) includes only a small number of commonly used instructions. This keeps the hardware small and, thus, fast.
- The instruction size is kept small to make instruction fetch fast.
(4) Good design demands good compromises.
- MIPS uses three instruction formats (instead of just one).
- Ideally all accesses would be as fast as a register access, but MIPS architecture
- also supports main memory accesses to allow for a compromise between fast access time and a large amount of memory.
- Because MIPS is a RISC architecture, it includes only a set of simple instructions, it provides pseudocode to the user and compiler for commonly used operations, like moving data from one register to another (move) and loading a 32-bit immediate (li).
Practice:
Q: Consider memory storage of a 32-bit word stored at memory word 15 in a byte- addressable memory, What is the byte address of memory word 15? (2 points)
A: 0x3C
Q:What are the byte addresses that memory word 15 spans? (2 points)
A:0x3C through 0x3F
Q: Draw the number 0xFF223344 stored at word 15 in both big-endian and little-endian machines. (4 points)
A:
Q:Write the MIPS Assembly code to write the value in $t4 into memory address 8
A: Store word:
sw $t4, 8($0)
Chapter 7 Microarchitecture
Recall that a computer architecture is defined by its instruction set and architectural state.
The architectural state for the MIPS processor consists of the program counter and the 32 registers.
To keep the microarchitectures easy to understand, we consider only
a subset of the MIPS instruction set. Specifically, we handle the following
instructions:
- R-type arithmetic/logic instructions: add, sub, and, or, slt
- Memory instructions: lw, sw
- Branches: beq
- extend them to handle addi and j
We will divide our microarchitectures into two interacting parts:
- The datapath: The datapath operates on words of data.
- The control: receives the current instruction from the datapath and tells the datapath how to execute that instruction.
A good way to design a complex system is to start with hardware
containing the state elements.
Figure 7.1 shows a block diagram with the four state elements: the program counter, register file, and instruction and data memories.
The program counter is an ordinary 32-bit register. Its output, PC,
points to the current instruction. Its input, PC′, indicates the address of
the next instruction.
The instruction memory has a single read port.1 It takes a 32-bit
instruction address input, A, and reads the 32-bit data (i.e., instruction)
from that address onto the read data output, RD.
The 32-element x 32-bit register file has two read ports and one write
port. The read ports take 5-bit address inputs, A1 and A2, each specifying
one of 25 = 32 registers as source operands. They read the 32-bit register
values onto read data outputs RD1 and RD2, respectively. The write port
takes a 5-bit address input, A3; a 32-bit write data input, WD; a write
enable input, WE3; and a clock. If the write enable is 1, the register file
writes the data into the specified register on the rising edge of the clock.
The instruction memory, register file, and data memory are all read combination-ally. In other words, if the address changes, the new data appears at RD after some propagation delay;
no clock is involved. They are written only on the rising edge of the clock.
In this fashion, the state of the system is changed only at the clock edge.
Because the state elements change their state only on the rising edge of the clock, they are synchronous sequential circuits
The microprocessor is built of clocked state elements and combinational logic, so it too is a synchronous sequential circuit.
In this chapter, we develop three microarchitectures for the MIPS processor
architecture: single-cycle, multicycle, and pipelined.
The single-cycle microarchitecture executes an entire instruction in one cycle. It is easy to explain and has a simple control unit. Because it completes the operation in one cycle, it does not require any nonarchitectural state. However, the cycle time is limited by the slowest instruction.
The multicycle microarchitecture executes instructions in a series of shorter cycles. Simpler instructions execute in fewer cycles than complicated ones. Moreover, the multicycle microarchitecture reduces the hardware cost by reusing expensive hardware blocks such as adders and memories. For example, the adder may be used on several different cycles for several purposes while carrying out a single instruction. The multicycle microprocessor accomplishes this by adding several non-architectural registers to hold intermediate results. The multicycle processor executes only one instruction at a time, but each instruction takes multiple clock cycles.
The pipelined microarchitecture applies pipelining to the single-cycle microarchitecture. It therefore can execute several instructions simultaneously, improving the throughput significantly. Pipelining must add logic to handle dependencies between simultaneously executing instructions. It also requires non-architectural pipeline registers. The added logic and registers are worthwhile; all commercial high-performance processors use pipelining today.
The cost depends on the amount of hardware required and the implementation technology.
in general, more gates and more memory mean more dollars.
The number of cycles per instruction, often called CPI, is the number of clock cycles required to execute an average instruction
This section presents HDL code for the single-cycle MIPS processor supporting all of the instructions discussed in this chapter, including addi and j.
Every 2 to 3 years, advances in CMOS manufacturing reduce transistor dimensions by 30% in each direction, doubling the number of transistors that can fit on a chip.
